/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/**
 * @file  dwmac_common.h
 * @brief Semidrive. AUTOSAR 4.3.1 MCAL Eth plugins.
 */
#ifndef MAC_COMMON_H
#define MAC_COMMON_H

#ifdef __cplusplus
extern "C" {
#endif

#include "RegHelper.h"
#include "Eth_GeneralTypes.h"
#include "Eth_PBCfg.h"

#if !defined(BIT)
#define BIT(n) ((uint32)(((uint32)1u) << (nr)))
#endif /** #if !defined(BIT) */

#if !defined(GENMASK)
#define GENMASK(h, l) \
    (((~0UL) - (1UL << (l)) + 1u) & (~0UL >> (32u - 1u - (h))))
#endif /** #if !defined(GENMASK) */


/*  MAC reg */
#define MAC_CONFIG              0x00000000
#define MAC_CONFIG_EXI          0x00000004
#define MAC_CONFIG_EXI_PDC      BIT(19)

#define MAC_PACKET_FILTER       0x00000008
#define MAC_HASH_TAB_0_31       0x00000010
#define MAC_HASH_TAB_32_63      0x00000014
#define MAC_HASH_TAB_64_95      0x00000018
#define MAC_HASH_TAB_96_127     0x0000001c

#define MAC_VLAN_TAG_CTRL       0x00000050
/* MAC VLAN regs */
#define MAC_VLAN_TAG_CTRL_OFS(x)    ((x << 2) & GENMASK(DWC_EQOS_RVFW + 1, 2))
#define MAC_VLAN_TAG_CTRL_CT        BIT(1)
#define MAC_VLAN_TAG_CTRL_OB        BIT(0)

#define MAC_VLAN_TAG_FILTER             0x00000054
#define MAC_VLAN_TAG_FILTER_DMACHN(x)   ((x << 25) & GENMASK(26, 25))
#define MAC_VLAN_TAG_FILTER_DMACHEN     BIT(24)
#define MAC_VLAN_TAG_FILTER_ETV         BIT(17)
#define MAC_VLAN_TAG_FILTER_VEN         BIT(16)
#define MAC_VLAN_TAG_FILTER_VID(x)      ((x << 0) & GENMASK(15, 0))

#define MAC_QX_TX_FLOW_CTRL(x)  (0x70 + x * 4)
#define MAC_RX_FLOW_CTRL        0x00000090
#define MAC_TXQ_PRTY_MAP0       0x98
#define MAC_TXQ_PRTY_MAP1       0x9C
#define MAC_RXQ_CTRL0           0x000000a0
#define MAC_RXQ_CTRL1           0x000000a4
#define MAC_RXQ_CTRL2           0x000000a8
#define MAC_RXQ_CTRL3           0x000000ac

#define MAC_INT_STATUS          0x000000b0
#define MAC_INT_STATUS_MMC_MASK    GENMASK(11, 8)

#define MAC_INT_EN              0x000000b4
#define MAC_RX_TX_STATUS        0x000000b8
#define MAC_LPI_CTRL_STATUS     0x000000d0
#define MAC_1US_TIC_COUNTER     0x000000dc
#define MAC_PCS_CONTROL         0x000000e0
#define MAC_PCS_STATUS          0x000000e4
#define MAC_PHYIF_CONTROL_STATUS    0x000000f8
#define MAC_PMT                 0x000000c0
#define MAC_VERSION             0x00000110
#define MAC_DEBUG               0x00000114
#define MAC_HW_FEATURE0         0x0000011c

#define MAC_HW_FEATURE1         0x00000120
#define MAC_HW_FEATURE1_PDUPSEL BIT(9)

#define MAC_HASH_TABLE_WIDTH_SHIFT     24
#define MAC_HASH_TABLE_WIDTH_MASK      GENMASK(25, 24)

#define MAC_TX_FIFO_SIZE_SHIFT          6
#define MAC_TX_FIFO_SIZE_MASK           GENMASK(10, 6)

#define MAC_RX_FIFO_SIZE_SHIFT          0
#define MAC_RX_FIFO_SIZE_MASK           GENMASK(4, 0)

#define MAC_HASH_TABLE_WIDTH_0      0x0
#define MAC_HASH_TABLE_WIDTH_64     0x1
#define MAC_HASH_TABLE_WIDTH_128    0x2
#define MAC_HASH_TABLE_WIDTH_256    0x3

#define MAC_HW_FEATURE2     0x00000124
#define MAC_HW_FEATURE3     0x00000128
#define MAC_MDIO_ADDR           0x00000200
#define MAC_MDIO_DATA           0x00000204
#define MAC_ADDR_HIGH(reg)      (0x300 + reg * 8)
#define MAC_ADDR_LOW(reg)       (0x304 + reg * 8)

/* MMC */
#define MAC_MMC_CTRL        0x700
#define MAC_MMC_CTRL_CNTPRSTLVL           BIT(5)
#define MAC_MMC_CTRL_CNTPRST           BIT(4)
#define MAC_MMC_CTRL_CNTFREEZ           BIT(3)
#define MAC_MMC_CTRL_RSTONRD           BIT(2)
#define MAC_MMC_CTRL_CNTSTOPRO           BIT(1)
#define MAC_MMC_CTRL_RESET           BIT(0)


#define MAC_MMC_RX_INTR_STA    0x704
#define MAC_MMC_RX_INTR_STA_MASK    GENMASK(27, 0)
#define MAC_MMC_TX_INTR_STA    0x708
#define MAC_MMC_TX_INTR_STA_MASK    GENMASK(27, 0)

#define MAC_MMC_RX_INTR_MASK    0x70c
#define MAC_MMC_TX_INTR_MASK    0x710
#define MAC_MMC_IPC_INTR_MASK    0x800
#define MAC_MMC_IPC_INTR_STA    0x808
/* Rx Stats */
#define MAC_PACKETS_RX_CONUT_64             0x000007ac
#define MAC_PACKETS_RX_CONUT_65_127         0x000007b0
#define MAC_PACKETS_RX_CONUT_128_255        0x000007b4
#define MAC_PACKETS_RX_CONUT_256_511        0x000007b8
#define MAC_PACKETS_RX_CONUT_512_1023       0x000007bc
#define MAC_PACKETS_RX_CONUT_1024_MAX       0x000007c0
#define MAC_PACKETS_RX_CONUT_UNICAST        0x000007c4
#define MAC_PACKETS_RX_CONUT_MULTICAST      0x00000790
#define MAC_PACKETS_RX_CONUT_BROADCAST      0x0000078c
#define MAC_PACKETS_RX_CONUT_ALL_BYTES      0x00000784
#define MAC_PACKETS_RX_CONUT_ALL_PKT        0x00000780
#define MAC_PACKETS_RX_CONUT_BAD_PKT        0x000007e0
#define MAC_PACKETS_RX_CONUT_CRC_ERR        0x00000794
#define MAC_PACKETS_RX_CONUT_FRAG_ERR       0x0000079C
#define MAC_PACKETS_RX_CONUT_ALIGN_ERR      0x00000798
#define MAC_PACKETS_RX_CONUT_JABBER_ERR     0x000007a0
#define MAC_PACKETS_RX_CONUT_UNDER_PKT      0x000007a4
#define MAC_PACKETS_RX_CONUT_OVER_PKT       0x000007a8
#define MAC_PACKETS_RX_CONUT_DROP_PKT       0x000007d4
#define MAC_PACKETS_RX_CONUT_MIIDROP_PKT    0x000007e0
/* Tx Stats */
#define MAC_PACKETS_TX_CONUT_ALL_BYTES      0x00000714
#define MAC_PACKETS_TX_CONUT_UNICAST        0x0000073C
#define MAC_PACKETS_TX_CONUT_BROADCAST      0x00000744
#define MAC_PACKETS_TX_CONUT_MULTICAST      0x00000740
#define MAC_PACKETS_TX_CONUT_SINGL_COLL     0x0000074C
#define MAC_PACKETS_TX_CONUT_MULT_COLL      0x00000750
#define MAC_PACKETS_TX_CONUT_DFRD_COLL      0x00000754
#define MAC_PACKETS_TX_CONUT_LATE_COLL      0x00000758
#define MAC_PACKETS_TX_CONUT_OVER_PKT       0x00000778
#define MAC_PACKETS_TX_CONUT_ALL_PKT        0x00000718
#define MAC_PACKETS_TX_CONUT_GOOD_BYTES     0x00000764
#define MAC_PACKETS_TX_CONUT_GOOD_PKT       0x00000768

#define MAC_PACKETS_TX_CONUT_DROP_PKT_COLL      0x0000075c
#define MAC_PACKETS_TX_CONUT_DROP_PKT_CARR      0x00000760
#define MAC_PACKETS_TX_CONUT_ERR_PKT        0x0000076c

/* RX Queues Routing */
#define MAC_RXQCTRL_AVCPQ_MASK      GENMASK(2, 0)
#define MAC_RXQCTRL_AVCPQ_SHIFT 0u
#define MAC_RXQCTRL_PTPQ_MASK       GENMASK(6, 4)
#define MAC_RXQCTRL_PTPQ_SHIFT      4u
#define MAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
#define MAC_RXQCTRL_DCBCPQ_SHIFT    8u
#define MAC_RXQCTRL_UPQ_MASK        GENMASK(14, 12)
#define MAC_RXQCTRL_UPQ_SHIFT       12u
#define MAC_RXQCTRL_MCBCQ_MASK      GENMASK(18, 16)
#define MAC_RXQCTRL_MCBCQ_SHIFT 16u
#define MAC_RXQCTRL_MCBCQEN     BIT(20)
#define MAC_RXQCTRL_MCBCQEN_SHIFT   20u
#define MAC_RXQCTRL_TACPQE      BIT(21)
#define MAC_RXQCTRL_TACPQE_SHIFT    21u

/* MAC Packet Filtering */
#define MAC_PACKET_FILTER_PR        BIT(0)
#define MAC_PACKET_FILTER_HUC       BIT(1)
#define MAC_PACKET_FILTER_HMC       BIT(2)
#define MAC_PACKET_FILTER_DAIF      BIT(3)
#define MAC_PACKET_FILTER_PM        BIT(4)
#define MAC_PACKET_FILTER_DBF       BIT(5)
#define MAC_PACKET_FILTER_MASK      GENMASK(7, 6)
#define MAC_PACKET_FILTER_SHIFT     (6u)
#define MAC_PACKET_FILTER_SAF       BIT(9)
#define MAC_PACKET_FILTER_HPF       BIT(10)
#define MAC_PACKET_FILTER_VTFE      BIT(16)
#define MAC_PACKET_FILTER_IPFE      BIT(20)
#define MAC_PACKET_FILTER_PA        BIT(31)

#define MAC_MAX_PERFECT_ADDRESSES   128u

/* MAC RX Queue Enable */
#define MAC_RX_QUEUE_CLEAR(queue)   (~(GENMASK(1, 0) << ((queue) * 2u)))
#define MAC_RX_AV_QUEUE_ENABLE(queue)   BIT((queue) * 2u)
#define MAC_RX_DCB_QUEUE_ENABLE(queue)  BIT(((queue) * 2u) + 1u)

/* MAC Flow Control RX */
#define MAC_RX_FLOW_CTRL_RFE        BIT(0)

/* RX Queues Priorities */
#define MAC_RXQCTRL_PSRQX_MASK(x)   GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
#define MAC_RXQCTRL_PSRQX_SHIFT(x)  ((x) * 8)

/* TX Queues Priorities */
#define MAC_TXQCTRL_PSTQX_MASK(x)   GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
#define MAC_TXQCTRL_PSTQX_SHIFT(x)  ((x) * 8)

/* MAC Flow Control TX */
#define MAC_TX_FLOW_CTRL_TFE        BIT(1)
#define MAC_TX_FLOW_CTRL_PT_SHIFT   16u

/*  MAC Interrupt bitmap*/

#define MAC_INT_RGSMIIS     BIT(0)
#define MAC_INT_PCS_LINK        BIT(1)
#define MAC_INT_PCS_ANE     BIT(2)
#define MAC_INT_PCS_PHYIS       BIT(3)
#define MAC_INT_PMT_EN          BIT(4)
#define MAC_INT_LPI_EN          BIT(5)

#define MAC_PCS_IRQ_DEFAULT (MAC_INT_RGSMIIS | MAC_INT_PCS_LINK |   \
                 MAC_INT_PCS_ANE)


#define MAC_STATUS_PMT          BIT(4)
#define MAC_STATUS_LPI          BIT(5)
#define MAC_STATUS_MMC_IPC      BIT(11)
#define MAC_STATUS_MMC_TX       BIT(10)
#define MAC_STATUS_MMC_RX       BIT(9)
#define MAC_STATUS_MMC          BIT(8)

/* MAC config */
#define MAC_CONFIG_IPC          BIT(27)
#define MAC_CONFIG_2K           BIT(22)
#define MAC_CONFIG_ACS          BIT(20)
#define MAC_CONFIG_WD           BIT(19)
#define MAC_CONFIG_BE           BIT(18)
#define MAC_CONFIG_JD           BIT(17)
#define MAC_CONFIG_JE           BIT(16)
#define MAC_CONFIG_PS           BIT(15)
#define MAC_CONFIG_FES          BIT(14)
#define MAC_CONFIG_DM           BIT(13)
#define MAC_CONFIG_LM           BIT(12)
#define MAC_CONFIG_DCRS         BIT(9)
#define MAC_CONFIG_TE           BIT(1)
#define MAC_CONFIG_RE           BIT(0)

/* L3_L4 filter */
#define MAC_L3_L4_CONTROL(x)        (0x00000900 + x * 0x30)
#define MAC_L3_L4_CONTROL_DMCHEN0   BIT(28)
#define MAC_L3_L4_CONTROL_DMCHN0(x) ((x << 24) & GENMASK(26, 24))
#define MAC_L3_L4_CONTROL_L4DPM0    BIT(20)
#define MAC_L3_L4_CONTROL_L4SPM0    BIT(18)
#define MAC_L3_L4_CONTROL_L4PEN0    BIT(16)

#define MAC_LAYER4_ADDRESS(x)       (0x00000904 + x * 0x30)
#define MAC_LAYER4_ADDRESS_L4DP0(x) ((x << 16) & GENMASK(31, 16))
#define MAC_LAYER4_ADDRESS_L4SP0(x) ((x << 0) & GENMASK(15, 0))

#define MAC_PTP_CONTRL          0x00000b00u
/* Timestamp Enable */
#define PTP_CONTRL_TSEN         BIT(0)
/* Timestamp Fine/Coarse Update */
#define PTP_CONTRL_TSCFUPDT     BIT(1)
/* Timestamp Initialize */
#define PTP_CONTRL_INIT         BIT(2)
/* Timestamp Update */
#define PTP_CONTRL_TSUPDT       BIT(3)
/* Timestamp Interrupt Trigger Enable */
#define PTP_CONTRL_TSTRIG       BIT(4)
/* Addend Reg Update */
#define PTP_CONTRL_TSADDREG     BIT(5)
/* Enable Timestamp for All Frames */
#define PTP_CONTRL_TSENALL      BIT(8)
/* Digital or Binary Rollover Control */
#define PTP_CONTRL_TSCTRLSSR    BIT(9)
/* Enable PTP packet Processing for Version 2 Format */
#define PTP_CONTRL_TSVER2ENA    BIT(10)
/* Enable Processing of PTP over Ethernet Frames */
#define PTP_CONTRL_TSIPENA      BIT(11)
/* Enable Processing of PTP Frames Sent over IPv6-UDP */
#define PTP_CONTRL_TSIPV6ENA    BIT(12)
/* Enable Processing of PTP Frames Sent over IPv4-UDP */
#define PTP_CONTRL_TSIPV4ENA    BIT(13)
/* Enable Timestamp Snapshot for Event Messages */
#define PTP_CONTRL_TSEVNTENA    BIT(14)
/* Enable Snapshot for Messages Relevant to Master */
#define PTP_CONTRL_TSMSTRENA    BIT(15)
/* Select PTP packets for Taking Snapshots
 * On gmac4 specifically:
 * Enable SYNC, Pdelay_Req, Pdelay_Resp when TSEVNTENA is enabled.
 * or
 * Enable  SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp,
 * Pdelay_Resp_Follow_Up if TSEVNTENA is disabled
 */
#define PTP_CONTRL_SNAPTYPSEL_1 BIT(16)
/* Enable MAC address for PTP Frame Filtering */
#define PTP_CONTRL_TSENMACADDR  BIT(18)
#define MAC_PTP_SSINC           0x00000b04
/* SSIR defines */
#define PTP_SSIR_SSINC_SHIFT    16u
#define MAC_PTP_SEC             0x00000b08
#define MAC_PTP_NSEC            0x00000b0C
#define PTP_NSEC_MASKE          GENMASK(30,0)
#define MAC_PTP_TSS             0x00000b10
#define MAC_PTP_TSSS            0x00000b14
#define MAC_PTP_TSAR            0x00000b18
#define MAC_PTP_TSHWR           0x00000b1c
/* MAC HW ADDR regs */
#define MAC_HI_DCS          GENMASK(18, 16)
#define MAC_HI_DCS_SHIFT        16u
#define MAC_HI_REG_AE(x)        (x << 31)
#define MAC_HI_REG_SA(x)        (x << 30)
#define MAC_HI_REG_DCS(x)       (x << 16)

/* EQOS MTL registers */
#define MTL_OP_MODE                     0x00000c00
#define MTL_OP_SCHALG_MASK              GENMASK(6, 5)
#define MTL_OP_SCHALG_WRR               (0x0 << 5)
#define MTL_OP_SCHALG_WFQ               (0x1 << 5)
#define MTL_OP_SCHALG_DWRR              (0x2 << 5)
#define MTL_OP_SCHALG_SP                (0x3 << 5)
#define MTL_OP_RAA                      BIT(2)
#define MTL_OP_RAA_SP                   (0x0 << 2)
#define MTL_OP_RAA_WSP                  (0x1 << 2)

#define MTL_TX_OPERATION_TSF            BIT(2)
#define MTL_TX_OPERATION_TQ             GENMASK(3, 2)
#define MTL_TX_OPERATION_TQ_EN          (0x2 << 2)
#define MTL_TX_OPERATION_TQ_DIS         (0x0 << 2)

#define MTL_TX_CONFIG_FLAGS_TQ          BIT(3)

#define MTL_INTR_STATUS                 0x00000c20
#define MTL_INTR_QXIS(x)                BIT(x)
#define MTL_INTR_ESTIS                  BIT(18)

/* MAP0 FOR queue 0 to 3; MAP1 for queue 4 to 7 */
#define MTL_RXQ_DMA_MAP0                0x00000c30
#define MTL_RXQ_DMA_MAP1                0x00000c34
#define MTL_RXQ_DMA_Q0MDMACH_MASK       GENMASK(3, 0)
#define MTL_RXQ_DMA_Q0MDMACH(x)         ((x) << 0)
#define MTL_RXQ_DMA_QXMDMACH_MASK(x)    GENMASK(3u + (8u * (x)), 8u * (x))
#define MTL_RXQ_DMA_QXMDMACH(Channel, q)    ((Channel) << (8u * (q)))
#define MTL_RXQ_DMA_Q04DDMACH(q)        (0x1u <<(4u+(8u * (q))))
#define MTL_RXQ_DMA_QXDDMACH(q)         (0x1 << (4u+(8u * ((q)-4u))))

#define MTL_TBS_CTRL            0x00000c40

#define MTL_EST_CTRL            0x00000c50
#define MTL_EST_PTOV            GENMASK(31, 24)
#define MTL_EST_PTOV_SHIFT      24
#define MTL_EST_SSWL            BIT(1)
#define MTL_EST_EEST            BIT(0)

#define MTL_EST_EXT_CTRL        0x00000c54

#define MTL_EST_STATUS              0x00000c58
#define MTL_EST_STATUS_BTRL         GENMASK(11, 8)
#define MTL_EST_STATUS_BTRL_SHIFT   8
#define MTL_EST_STATUS_BTRL_MAX     (0xF << BTRL_SHIFT)
#define MTL_EST_STATUS_SWOL         BIT(7)
#define MTL_EST_STATUS_SWOL_SHIFT   7
#define MTL_EST_STATUS_CGCE         BIT(4)
#define MTL_EST_STATUS_HLBS         BIT(3)
#define MTL_EST_STATUS_HLBF         BIT(2)
#define MTL_EST_STATUS_BTRE         BIT(1)
#define MTL_EST_STATUS_SWLC         BIT(0)

#define MTL_EST_INT_EN          0x00000c70
#define MTL_EST_INT_IECGCE      MTL_EST_STATUS_CGCE
#define MTL_EST_INT_IEHS        MTL_EST_STATUS_HLBS
#define MTL_EST_INT_IEHF        MTL_EST_STATUS_HLBF
#define MTL_EST_INT_IEBE        MTL_EST_STATUS_BTRE
#define MTL_EST_INT_IECC        MTL_EST_STATUS_SWLC
#define MTL_EST_INT_ALL         (MTL_EST_STATUS_SWLC | MTL_EST_STATUS_BTRE | \
                                 MTL_EST_STATUS_HLBF | MTL_EST_STATUS_HLBS | \
                                 MTL_EST_STATUS_CGCE)

#define MTL_EST_GCL_CTRL        0x00000c80
#define MTL_EST_GCL_BTR_LOW     0x0
#define MTL_EST_GCL_BTR_HIGH    0x1
#define MTL_EST_GCL_CTR_LOW     0x2
#define MTL_EST_GCL_CTR_HIGH    0x3
#define MTL_EST_GCL_TER         0x4
#define MTL_EST_GCL_LLR         0x5
#define MTL_EST_GCL_ADDR_SHIFT  8
#define MTL_EST_GCL_GCRR        BIT(2)
#define MTL_EST_GCL_SRWO        BIT(0)

#define MTL_EST_GCL_DATA        0x00000c84
#define MTL_EST_GCL_GC_TC2      BIT(18)
#define MTL_EST_GCL_GC_TC1      BIT(17)
#define MTL_EST_GCL_GC_TC0      BIT(16)
#define MTL_EST_GCL_TIME(x)     ((x << 0) & GENMASK(15, 0))

#define GCL_CTRL_PTOV           GENMASK(31, 24)
#define GCL_CTRL_PTOV_SHIFT     24U
#define GCL_CTRL_SSWL           BIT(1)
#define GCL_CTRL_EEST           BIT(0)
#define GCL_CTRL_REG_BTR_LOW    0x0
#define GCL_CTRL_REG_BTR_HIGH   0x1
#define GCL_CTRL_REG_CTR_LOW    0x2
#define GCL_CTRL_REG_CTR_HIGH   0x3
#define GCL_CTRL_REG_TER        0x4
#define GCL_CTRL_REG_LLR        0x5

#define GCL_CTRL_ADDR_SHIFT     8U
#define GCL_CTRL_SRWO           BIT(0)
#define GCL_CTRL_GCRR           BIT(2)
#define MTL_EST_GCL_DATA        0x00000c84
#define MTL_ECC_STATUS          0x00000ccc

#define MTL_ECC_CTRL            0x00000cc0
#define MTL_ECC_DEFAULT_ENABLE        GENMASK(3, 0)

#define MTL_ECC_INT_EN            0x00000cc8
#define MTL_ECC_COR_ERR_EST        BIT(8)
#define MTL_ECC_COR_ERR_RX         BIT(4)
#define MTL_ECC_COR_ERR_TX         BIT(0)

#define MTL_DPP_CTRL            0x00000ce0
#define MTL_DPP_CTRL_DATA_PARITY         BIT(0)
#define MTL_DPP_CTRL_SLAVE_PARITY        BIT(2)


#define MTL_QUEUE_BASE_ADDR         0x00000d00
#define MTL_QUEUE_BASE_OFFSET       0x40u
#define MTL_QUEUEX_BASE_ADDR(x)     (MTL_QUEUE_BASE_ADDR + \
                    (x * MTL_QUEUE_BASE_OFFSET))

#define MTL_QUEUE_TX_OP_MODE(x)     MTL_QUEUEX_BASE_ADDR(x)
#define MTL_QUEUE_TX_DEBUG(x)       (MTL_QUEUEX_BASE_ADDR(x) + 0x8)
#define MTL_QUEUE_EST_CTRL(x)       (MTL_QUEUEX_BASE_ADDR(x) + 0x10)
#define MTL_QUEUE_TX_WEIGHT(x)      (MTL_QUEUEX_BASE_ADDR(x) + 0x18)
#define MTL_QUEUE_TX_SSC(x)         (MTL_QUEUEX_BASE_ADDR(x) + 0x1c)
#define MTL_QUEUE_TX_HC(x)          (MTL_QUEUEX_BASE_ADDR(x) + 0x20)
#define MTL_QUEUE_TX_LC(x)          (MTL_QUEUEX_BASE_ADDR(x) + 0x24)
#define MTL_QUEUE_INT_CTRL(x)       (MTL_QUEUEX_BASE_ADDR(x) + 0x2c)
#define MTL_QUEUE_RX_OP_MODE(x)     (MTL_QUEUEX_BASE_ADDR(x) + 0x30)
#define MTL_QUEUE_RX_DEBUG(x)       (MTL_QUEUEX_BASE_ADDR(x) + 0x38)

#define MTL_TXQ_OP_MODE_TXQEN_MASK  GENMASK(3, 2)
#define MTL_TXQ_OP_MODE_TXQEN_AV    BIT(2)
#define MTL_TXQ_OP_MODE_TXQEN       BIT(3)
#define MTL_TXQ_OP_MODE_TSF         BIT(1)

#define MTL_TXQ_OP_MODE_TQS_MASK    GENMASK(24, 16)
#define MTL_TXQ_OP_MODE_TQS_SHIFT   16u
#define MTL_TXQ_OP_MODE_TTC_MASK    0x70u
#define MTL_TXQ_OP_MODE_TTC_SHIFT   4u
#define MTL_TXQ_OP_MODE_TTC_32      0u
#define MTL_TXQ_OP_MODE_TTC_64      (1 << MTL_TXQ_OP_MODE_TTC_SHIFT)
#define MTL_TXQ_OP_MODE_TTC_96      (2 << MTL_TXQ_OP_MODE_TTC_SHIFT)
#define MTL_TXQ_OP_MODE_TTC_128     (3 << MTL_TXQ_OP_MODE_TTC_SHIFT)
#define MTL_TXQ_OP_MODE_TTC_192     (4 << MTL_TXQ_OP_MODE_TTC_SHIFT)
#define MTL_TXQ_OP_MODE_TTC_256     (5 << MTL_TXQ_OP_MODE_TTC_SHIFT)
#define MTL_TXQ_OP_MODE_TTC_384     (6 << MTL_TXQ_OP_MODE_TTC_SHIFT)
#define MTL_TXQ_OP_MODE_TTC_512     (7 << MTL_TXQ_OP_MODE_TTC_SHIFT)

#define MTL_RXQ_OP_MODE_RQS_MASK    GENMASK(29, 20)
#define MTL_RXQ_OP_MODE_RQS_SHIFT   20u
#define MTL_RXQ_OP_MODE_RFD_MASK    GENMASK(19, 14)
#define MTL_RXQ_OP_MODE_RFD_SHIFT   14u
#define MTL_RXQ_OP_MODE_RFA_MASK    GENMASK(13, 8)
#define MTL_RXQ_OP_MODE_RFA_SHIFT   8u
#define MTL_RXQ_OP_MODE_EHFC        BIT(7)
#define MTL_RXQ_OP_MODE_RSF         BIT(5)
#define MTL_RXQ_OP_MODE_FEP         BIT(4)
#define MTL_RXQ_OP_MODE_FUP         BIT(3)

/* MTL TXQ ETS Control */
#define MTL_TXQ_ETS_CTRL_SLC        GENMASK(6, 4)
#define MTL_TXQ_ETS_CTRL_SLC_OFFSET 4U
#define MTL_TXQ_ETS_CTRL_CC         BIT(3)
#define MTL_TXQ_ETS_CTRL_AVALG      BIT(2)

/* MTL TXQ Quantum Weight */
#define MTL_TXQ_QT_WEIGHT_ISCQW_MASK    GENMASK(20, 0)

/* MTL TXQ sendSlopeCredit */
#define MTL_TXQ_SEND_SLP_CRED_SSC_MASK  GENMASK(13, 0)

/* MTL TXQ hiCredit  */
#define MTL_TXQ_HIGH_CRED_HC_MASK       GENMASK(28, 0)

/* MTL TXQ loCredit */
#define MTL_TXQ_LOW_CRED_LC_MASK        GENMASK(28, 0)

/*  MTL Q interrupt */
#define MTL_Q_INT_CTRL_RXOIE        BIT(24)
#define MTL_Q_INT_CTRL_RXOVFIS      BIT(16)
#define MTL_Q_INT_CTRL_TXUNFIS      BIT(0)

/* Default operating mode of the MAC */
#define MAC_CORE_INIT (MAC_CONFIG_JD | MAC_CONFIG_PS | \
            MAC_CONFIG_BE | MAC_CONFIG_DCRS | MAC_CONFIG_DM)

/* To dump the core regs excluding  the Address Registers */
#define MAC_REG_NUM 0x300

/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR    0x0u
#define MTL_TX_ALGORITHM_WFQ    0x1u
#define MTL_TX_ALGORITHM_DWRR   0x2u
#define MTL_TX_ALGORITHM_SP     0x3u
#define MTL_RX_ALGORITHM_SP     0x4u
#define MTL_RX_ALGORITHM_WSP    0x5u
#define MTL_TX_ALGORITHM_CC     0x6u
/* RX/TX Queue Mode */
#define MTL_QUEUE_MODE_AVB      0x1u
#define MTL_QUEUE_MODE_DCB      0x2u

#define MTL_ALGORITHM_WRR_MAX 0x64
#define MTL_ALGORITHM_WFQ_MAX 0x3fff
#define MTL_ALGORITHM_DWRR_MAX 0x1312D0

#define MTL_ALGORITHM_WRR_BASE 10u
#define MTL_ALGORITHM_WFQ_BASE 1638u
#define MTL_ALGORITHM_DWRR_BASE 125000

#define SF_MODE  1

#define MAC_FITER_PASS_ALL                  0u
#define MAC_FITER_PASS_MULTICAST            1u
#define MAC_FITER_PASS_HASH_MULTICAST       2u
#define MAC_FITER_PASS_UNICAST              3u

#define ERDES4_MSG_TYPE_MASK        GENMASK(11, 8)
/* Extended RDES4 message type definitions */
#define RDES_EXT_NO_PTP         0x0u
#define RDES_EXT_SYNC           0x1u
#define RDES_EXT_FOLLOW_UP      0x2u
#define RDES_EXT_DELAY_REQ      0x3u
#define RDES_EXT_DELAY_RESP     0x4u
#define RDES_EXT_PDELAY_REQ     0x5u
#define RDES_EXT_PDELAY_RESP        0x6u
#define RDES_EXT_PDELAY_FOLLOW_UP   0x7u
#define RDES_PTP_ANNOUNCE       0x8u
#define RDES_PTP_MANAGEMENT     0x9u
#define RDES_PTP_SIGNALING      0xau
#define RDES_PTP_PKT_RESERVED_TYPE  0xfu

/* Rx IPC status */
enum rx_frame_status {
    RX_GOOD = 0x0u,
    RX_BAD = 0x1u,
    RX_DMA_PROCESS = 0x2u,
};

enum {
    PHY_SPEED_10 = 0x0u,
    PHY_SPEED_100 = 0x1u,
    PHY_SPEED_1000= 0x2u,
};


enum tx_frame_status {
    TX_GOOD = 0x0u,
    TX_ERROR = 0x1u,
    TX_DMA_PROCESS = 0x2u,
    TX_NOT_LS = 0x3u,
};

/* DMA Mode */
#define DMA_MODE                    0x00001000
#define DMA_MODE_INTM_MASK          GENMASK(17,16)
#define DMA_MODE_INTM_SHIFT         16U
#define DMA_MODE_INTM_LEVEL         (0x01u << DMA_MODE_INTM_SHIFT)
#define DMA_BUS_TAA_MASK            GENMASK(4,2)
#define DMA_BUS_TAA_SHIFT           2u
#define DMA_BUS_MODE_SFT_RESET      BIT(0)

#define DMA_BUS_TAA_WRR             0x2u
#define DMA_BUS_TAA_WSP             0x1u
#define DMA_BUS_TAA_FP              0x0u

/* DMA SYS Bus Mode */
#define DMA_SYSBUS_MODE             0x00001004

#define DMA_SYSBUS_EN_LPI           BIT(31)
#define DMA_SYSBUS_LPI_XIT_FRM      BIT(30)
#define DMA_SYSBUS_WR_OSR_LMT       GENMASK(27, 24)
#define DMA_SYSBUS_WR_OSR_LMT_SHIFT    24u
#define DMA_SYSBUS_RD_OSR_LMT       GENMASK(19, 16)
#define DMA_SYSBUS_RD_OSR_LMT_SHIFT    16u

#define DMA_SYSBUS_OSR_MAX          0xfu
#define DMA_SYSBUS_MAX_OSR_LIMIT ((DMA_SYSBUS_OSR_MAX << DMA_SYSBUS_WR_OSR_LMT_SHIFT) | \
                (DMA_SYSBUS_OSR_MAX << DMA_SYSBUS_RD_OSR_LMT_SHIFT))

#define DMA_SYSBUS_MB               BIT(14)
#define DMA_SYSBUS_1KBBE            BIT(13)
#define DMA_SYSBUS_AAL              BIT(12)
#define DMA_SYSBUS_EAME             BIT(11)
#define DMA_SYSBUS_BLEN256          BIT(7)
#define DMA_SYSBUS_BLEN128          BIT(6)
#define DMA_SYSBUS_BLEN64           BIT(5)
#define DMA_SYSBUS_BLEN32           BIT(4)
#define DMA_SYSBUS_BLEN16           BIT(3)
#define DMA_SYSBUS_BLEN8            BIT(2)
#define DMA_SYSBUS_BLEN4            BIT(1)
#define DMA_SYSBUS_FB               BIT(0)

#define DMA_AXI_SYS_MASK    (DMA_SYSBUS_FB      \
                             | DMA_SYSBUS_MB     \
                             | DMA_SYSBUS_AAL    \
                             | DMA_SYSBUS_EAME   \
                             | DMA_SYSBUS_BLEN256    \
                             | DMA_SYSBUS_BLEN128    \
                             | DMA_SYSBUS_BLEN64     \
                             | DMA_SYSBUS_BLEN32     \
                             | DMA_SYSBUS_BLEN16     \
                             | DMA_SYSBUS_BLEN8      \
                             | DMA_SYSBUS_BLEN4)

#define DMA_INT_STATUS              0x00001008
#define DMA_DEBUG_STATUS0           0x0000100c
#define DMA_DEBUG_STATUS1           0x00001010
#define DMA_DEBUG_STATUS2           0x00001014
enum dma_rx_status {
    DMX_RX_STOP = 0u,
    DMX_RX_RUN_FRTD = 1u,
    DMX_RX_RSVD = 2u,
    DMX_RX_WRP = 3u,
    DMX_RX_SUSPND = 4u,
    DMX_RX_RUN_CRD = 5u,
    DMX_RX_TSTMP = 6u,
    DMX_RX_TRP = 7u
};

/* DMA Interrupt status */
#define DMA_INT_STATUS_MAC          BIT(17)
#define DMA_INT_STATUS_MTL          BIT(16)
#define DMA_INT_STATUS_CHAN7        BIT(7)
#define DMA_INT_STATUS_CHAN6        BIT(6)
#define DMA_INT_STATUS_CHAN5        BIT(5)
#define DMA_INT_STATUS_CHAN4        BIT(4)
#define DMA_INT_STATUS_CHAN3        BIT(3)
#define DMA_INT_STATUS_CHAN2        BIT(2)
#define DMA_INT_STATUS_CHAN1        BIT(1)
#define DMA_INT_STATUS_CHAN0        BIT(0)
#define DMA_INT_STATUS_CHAN0_5      GENMASK(4,0)

#define HASH_TABLE_IDX(x)           ((uint32)(((x)>>5u)*4u))
#define HASH_REG_MASK(x)            ((uint32)(0x01u<<(x%32u)))

#define DMA_BURST_LEN_DEFAULT       (DMA_SYSBUS_BLEN16 | DMA_SYSBUS_BLEN8 | DMA_SYSBUS_BLEN4)

#define DEFAULT_DMA_SYS  (DMA_SYSBUS_AAL|DMA_SYSBUS_MAX_OSR_LIMIT|DMA_BURST_LEN_DEFAULT)

/* DMA CH control defines */
#define DMA_CH_BASE_ADDR            0x00001100
#define DMA_CH_BASE_OFFSET          0x80u
#define DMA_CHX_BASE_ADDR(x)        (DMA_CH_BASE_ADDR + \
                                     (x * DMA_CH_BASE_OFFSET))

#define DMA_CH_CONTROL(x)           DMA_CHX_BASE_ADDR(x)
#define DMA_CH_TX_CONTROL(x)        (DMA_CHX_BASE_ADDR(x) + 0x4)
#define DMA_CH_RX_CONTROL(x)        (DMA_CHX_BASE_ADDR(x) + 0x8)
#define DMA_CH_TX_BASE_ADDR_HI(x)   (DMA_CHX_BASE_ADDR(x) + 0x10)
#define DMA_CH_TX_BASE_ADDR(x)      (DMA_CHX_BASE_ADDR(x) + 0x14)
#define DMA_CH_RX_BASE_ADDR_HI(x)   (DMA_CHX_BASE_ADDR(x) + 0x18)
#define DMA_CH_RX_BASE_ADDR(x)      (DMA_CHX_BASE_ADDR(x) + 0x1c)
#define DMA_CH_TX_END_ADDR(x)       (DMA_CHX_BASE_ADDR(x) + 0x20)
#define DMA_CH_RX_END_ADDR(x)       (DMA_CHX_BASE_ADDR(x) + 0x28)
#define DMA_CH_TX_RING_LEN(x)       (DMA_CHX_BASE_ADDR(x) + 0x2c)
#define DMA_CH_RX_RING_LEN(x)       (DMA_CHX_BASE_ADDR(x) + 0x30)
#define DMA_CH_INTR_ENA(x)          (DMA_CHX_BASE_ADDR(x) + 0x34)
#define DMA_CH_RX_WATCHDOG(x)       (DMA_CHX_BASE_ADDR(x) + 0x38)
#define DMA_CH_CUR_TX_DESC(x)       (DMA_CHX_BASE_ADDR(x) + 0x44)
#define DMA_CH_CUR_RX_DESC(x)       (DMA_CHX_BASE_ADDR(x) + 0x4c)
#define DMA_CH_CUR_TX_BUF_ADDR(x)   (DMA_CHX_BASE_ADDR(x) + 0x54)
#define DMA_CH_CUR_RX_BUF_ADDR(x)   (DMA_CHX_BASE_ADDR(x) + 0x5c)
#define DMA_CH_STATUS(x)            (DMA_CHX_BASE_ADDR(x) + 0x60)

/* DMA Channel X Control */
#define DMA_CH_CTRL_SPH             BIT(24)
#define DMA_CH_CTRL_DSL_MASK        GENMASK(20, 18)
#define DMA_CH_CTRL_DSL_SHIFT       18u
#define DMA_CH_CTRL_PBL             BIT(16)
#define DMA_CH_CTRL_PBL_SHIFT       16u
#define DMA_CH_CTRL_MSS_MASK        GENMASK(13, 0)

/* DMA Channel X Tx Control */
#define DMA_CH_TX_CTRL_TQOS_MASK    GENMASK(27, 24)
#define DMA_CH_TX_CTRL_TQOS_SHIFT   24u
#define DMA_CH_TX_CTRL_PBL_MASK     GENMASK(21,16)
#define DMA_CH_TX_CTRL_RPBL_SHIFT   16u
#define DMA_CH_TX_CTRL_TSE          BIT(12)
#define DMA_CH_TX_CTRL_OSP          BIT(4)
#define DMA_CH_TX_CTRL_TCW_MASK     GENMASK(3, 1)
#define DMA_CH_TX_CTRL_TCW_SHIFT    1u
#define DMA_CH_TX_CTRL_ST           BIT(0)

/* DMA Channel X Rx Control */
#define DMA_CH_RX_CTRL_RPF          BIT(31)
#define DMA_CH_RX_CTRL_SR           BIT(0)
#define DMA_CH_RX_CTRL_RBSZ_MASK    GENMASK(14, 1)
#define DMA_CH_RX_CTRL_RBSZ_SHIFT   1u

/* DMA Channel X Status */
#define DMA_CH_STATUS_REB           GENMASK(21, 19)
#define DMA_CH_STATUS_REB_SHIFT     19u
#define DMA_CH_STATUS_TEB           GENMASK(18, 16)
#define DMA_CH_STATUS_TEB_SHIFT     16u
#define DMA_CH_STATUS_NIS           BIT(15)
#define DMA_CH_STATUS_AIS           BIT(14)
#define DMA_CH_STATUS_CDE           BIT(13)
#define DMA_CH_STATUS_FBE           BIT(12)
#define DMA_CH_STATUS_ERI           BIT(11)
#define DMA_CH_STATUS_ETI           BIT(10)
#define DMA_CH_STATUS_RWT           BIT(9)
#define DMA_CH_STATUS_RPS           BIT(8)
#define DMA_CH_STATUS_RBU           BIT(7)
#define DMA_CH_STATUS_RI            BIT(6)
#define DMA_CH_STATUS_TBU           BIT(2)
#define DMA_CH_STATUS_TPS           BIT(1)
#define DMA_CH_STATUS_TI            BIT(0)

#define DMA_CH_STATUS_PERCH   (DMA_CH_STATUS_AIS|DMA_CH_STATUS_RBU |\
                                DMA_CH_STATUS_TI|DMA_CH_STATUS_RI|\
                                DMA_CH_STATUS_TBU|DMA_CH_STATUS_ERI)

/* DMA CH X Interrupt Enable */
#define DMA_CH_INTR_EN_NIE          BIT(15)
#define DMA_CH_INTR_EN_AIE          BIT(14)
#define DMA_CH_INTR_EN_CDE          BIT(13)
#define DMA_CH_INTR_EN_FBE          BIT(12)
#define DMA_CH_INTR_EN_ERE          BIT(11)
#define DMA_CH_INTR_EN_ETE          BIT(10)
#define DMA_CH_INTR_EN_RWE          BIT(9)
#define DMA_CH_INTR_EN_RSE          BIT(8)
#define DMA_CH_INTR_EN_RBUE         BIT(7)
#define DMA_CH_INTR_EN_RIE          BIT(6)
#define DMA_CH_INTR_EN_TBUE         BIT(2)
#define DMA_CH_INTR_ENATSE          BIT(1)
#define DMA_CH_INTR_EN_TIE          BIT(0)

#define DMA_CH_INTR_NORMAL          (DMA_CH_INTR_EN_NIE | \
                                     DMA_CH_INTR_EN_RIE | \
                                     DMA_CH_INTR_EN_RBUE| \
                                     DMA_CH_INTR_EN_TIE )

#define DMA_CH_INTR_ABNORMAL        (DMA_CH_INTR_EN_AIE | \
                                     DMA_CH_INTR_EN_FBE|DMA_CH_INTR_EN_RSE)
/* DMA CH default interrupt mask */
#define DMA_CH_INTR_DEFAULT_MASK    (DMA_CH_INTR_NORMAL | \
                                     DMA_CH_INTR_ABNORMAL)

#define PHY_CLAUSE_22   0xFFu

struct est_btr {
    uint32 seconds;
    uint32 nano_seconds;
};

struct est_ctr {
    uint8 seconds;
    uint32 nano_seconds;
};

#define EST_GCL     64u
struct stmmac_est {
    struct est_btr btr;
    struct est_ctr ctr;
    uint32 ter;
    uint32 *gcl;
    uint32 gcl_size;
};

/*
    mode  transmit store and forward enable or not
    qmode transmit queue enable or not
    fifo  transmit queue size
*/
#if defined(DEBUG_ENABLE)
void dwmac_dump_mac(uint32   addr);
void dwmac_dump_mtl(uint32  regbase, uint32 queue);
#endif
void dwmac_prog_mtl_rx_algorithms(uint32  regbase, uint32 rx_alg);
void dwmac_prog_mtl_tx_algorithms(uint32  regbase, uint32 tx_alg);
void dwmac_map_mtl_dma(uint32  addr, uint32 queue, uint32 Channel);
sint32 dwmac_set_filter(uint32  regbase, uint32 mode, const uint8 *mac_addr);
sint32 init_systime(uint32 RegBase, uint32 sec, uint32 nsec);
void get_systime(uint32 RegBase, uint32 *sec, uint32 *nsec);
void dwmac_flow_ctrl(uint32  regbase, uint32 duplex, uint32 fc,
                     uint32 pause_time, uint32 tx_cnt);
int dwmac5_est_configure(uint32 RegBase, struct stmmac_est *cfg,
                         unsigned int ptp_rate, boolean enable);
void dwmac_core_init(uint32 RegBase, uint32 MTU, uint32 mac_high, uint32 mac_low, uint32 Speed);
#if (ETH_DIRECT_FORWARD_ENABLE == STD_ON)
void dwmac_set_filter_enable(uint32 RegBase, uint32 value);
void dwmac_set_packet_dup_enable(uint32 RegBase);
boolean dwmac_get_packet_dup_enable(uint32 RegBase);
void dwmac_set_mac_filter(uint32 RegBase, uint32 macHigh, uint32 macLow,
                          uint32 Reg_n, uint32 DmaChSelect,
                          boolean AddrEnable, boolean SourceAddr);
void dwmac_set_vlan_filter(uint32 RegBase, uint16 vlan,
                           uint32 Reg_n, uint32 DmaChSelect);
void dwmac_set_port_filter(uint32 RegBase, const Eth_PortFilterConfigType* portFilter,
                           uint32 Reg_n, uint32 DmaChSelect);
void dwmac_disable_specify_dma_irq(uint32 RegBase, uint32 Channel, boolean rx);
#endif
void dwmac_set_umac_addr(uint32  regbase, const uint8 *addr, uint32 reg_n);
void dwmac_get_umac_addr(uint32  regbase, uint8 *addr, uint32 reg_n);
void rx_stats_update(uint32  RegBase, Eth_RxStatsType *Stats);
void tx_stats_update(uint32  RegBase, Eth_TxStatsType *Stats);
void controller_counter_update(uint32 RegBase, Eth_CounterType *Stats);
void tx_error_count_update(uint32  RegBase, Eth_TxErrorCounterValuesType *count);
void mac_irq_handler(uint8 CtrlIdx,uint32  RegBase);
void dwmac_rx_queue_enable(uint32  addr, uint32 mode, uint32 queue);
int dwmac_irq_mtl_status(uint32  regbase, uint32 Channel);
sint32 dwmac_dma_reset(uint32  regbase);
boolean dwmac_access_test(uint32  regbase);
void dwmac_enable_dma_irq(uint32  regbase, uint32 Channel, boolean rx, boolean tx);
void dwmac_dma_start_tx(uint32  regbase, uint32 Channel);
void dwmac_dma_stop_tx(uint32  regbase, uint32 Channel);
void dwmac_dma_start_rx(uint32  regbase, uint32 Channel);
void dwmac_dma_stop_rx(uint32  regbase, uint32 Channel);
void dwmac_dma_rx_chan_op_mode(uint32  regbase, uint32 channel,
                               int fifosz, uint32 qmode);
void dwmac_set_clock_delay(uint32 RegBase, boolean rxDelay, boolean txDelay);
/*
    mode  transmit store and forward enable or not
    qmode transmit queue enable or not
    fifo  transmit queue size
*/
void dwmac_dma_tx_chan_op_mode(uint32  regbase, uint32 channel,
                               uint32 fifosz, uint32 qmode);

void dwmac_set_rx_ring_len(uint32  regbase, uint32 len, uint32 Channel);
void dwmac_set_tx_ring_len(uint32  regbase, uint32 len, uint32 Channel);
void dwmac_set_rx_tail_ptr(uint32  regbase, uint32   tail_ptr, uint32 Channel);
void dwmac_set_tx_tail_ptr(uint32  regbase, uint32   tail_ptr, uint32 Channel);
void dwmac_dma_init_rx_chan(uint32  regbase, uint32   base_ptr, uint32 Channel);
void dwmac_dma_init_tx_chan(uint32  regbase, uint32   base_ptr, uint32 Channel);
void dwmac_dma_bus_init(uint32  regbase, uint32 flags);
enum dma_rx_status dwmac_dma_rx_state_get(uint32 RegBase, uint32 Channel);
void dwmac_dma_init_channel(uint32  regbase,uint32 Channel, uint32 skip);

void dwmac_set_bfsize(uint32  regbase, uint32 mtu, uint32 Channel);
sint32 mac_mdio_write(uint32  regbase, uint8 PhyAddr, uint8 device, uint16 phyreg, uint16 phydata);
sint32 mac_mdio_read(uint32  regbase, uint8 PhyAddr, uint8 device, uint16 phyreg);
void dwmac_rx_trigger(uint32  RegBase, uint32 Channel);
void dwmac_mac_rx_queue_mcbc_routing(uint32  RegBase, uint8 Channel);

void config_sub_second_increment(uint32 regbase, uint32 ptp_clock);
void dwmac_init_systime(uint32 regbase, uint32 sec, uint32 nsec);
void dwmac_get_time(uint32 regbase, uint32 *sec, uint32 *nsec);
void setup_timestamp_filter(uint32 regbase, ptp_version_t ptp_v,
                            ptp_mode_t is_ptp_master, ptp_rx_filter_t rxfilter);
void dwmac_mtl_tx_chan_set_weight(uint32 RegBase,uint32 Algorithms ,uint32 Channel, uint32 weight);

void dwmac_mtl_tx_chan_set_cbs(uint32 RegBase, uint32 Channel,
                               uint32 isc, uint32 ssc, uint32 hc, uint32 lc);
void dwmac_mtl_tx_chan_set_sp_mode(uint32 RegBase, uint32 Channel);

void dwmac_dma_tx_chan_weight(uint32 RegBase, uint32 Channel, uint32 twc);

void dwmac_mac_stop_tx(uint32 RegBase);

void dwmac_mac_start_tx(uint32 RegBase);

void dwmac_disable_all_irqs(uint32 RegBase, uint32 Channel);

#ifdef __cplusplus
}
#endif

#endif
